The present invention is directed to signal responses in electronic devices, and especially to non-linearity responses in electronic devices such as analog-to-digital converters.
Many ADC (Analog-to-Digital Converter) architectures implement a quantization process comprised of multiple stages to incrementally resolve the digital representation of an analog signal. Such architectures are sometimes referred to as a pipeline ADC architecture. Whether the pipeline architecture is based on switched-capacitor or a switched-current approach, the linearity—and thus the distortion performance—of the ADC is impacted by the degree of matching among components found in the local quantization circuit of each stage.
Switched-current designs will suffer from mismatches between the elements of the folding sub-ADC, and mismatches between the current sources elements constituting the reconstruction DAC (Digital-to-Analog Converter). The DAC could be segmented in different ways to vary the impact of the mismatch (e.g., unary versus binary-weighted sources). However, once a mismatch among the elementary DAC elements has been minimized, the relative current mismatch among stages comes into play.
In switched-capacitor ADC implementations the relative size of the capacitors determines the gain of a stage along with the size of the voltage steps in the local reconstruction MDAC (Multiplying Digital-to-Analog Converter), directly impacting the integral non-linearity (INL). INL describes the departure by a device, such as an ADC device, from an ideal linear transfer curve. INL is a measure of the straightness of the transfer function of the device. These technology-related mismatches among components in a device have become important in the latest releases of minimum-feature CMOS (Complementary Metal Oxide Semiconductor) processes, where the lithographic control over active and passive devices is difficult to achieve.
Techniques have been devised which employ analog or digital solutions to correct for mismatch errors. Bit-redundancy techniques have proven effective for taking care of the sub-ADC imperfections. The sub-DACs non-idealities have instead been tackled either via digital calibration methods (e.g., one-time adjustments, or continuous background calibration); or via an analog “trimming” of the devices impacted by the statistical mismatch. The trimming techniques are based on the identification of the errors affecting the INL (e.g., bowing, S-shapes, positive or negative gaps). Once the amount of the non-ideality has been assessed, the passive components determining the ADC behavior are trimmed, or adjusted, to compensate for the errors. For example, selective laser cuts can trim the value of resistors in a DAC to linearize the analog signal translation from the digital word. Alternately, tiny parasitic capacitors can be switched in parallel to the signal capacitors of a quantizer's stages to counter any mismatch, such as a process-induced component mismatch.
Digital treatment of signals is an effective approach to effecting trimming or other adjustments to a circuit for the purpose of obviating or reducing component mismatch errors, such as by trimming or by selective capacitor inclusion. Accurate treatment of a problem having analog origins, such as many component mismatch errors, using a digital signal treatment requires an accurate digital representation of analog signals and processes to be corrected.
There is a need for a method for digitally representing an analog signal such as integral non-linearity response for a device.